Variable Record Table: A Run-time Solution for Mitigating Buffer Overflow Attack

We present a novel approach to mitigate buffer overflow attack using Variable Record Table (VRT). Dedicated memory space is used to automatically record base and bound information of variables extracted during runtime. We instrument frame pointer and function(s) related registers to decode variable memory space in stack and heap. We have modified Simplescalar/PISA simulator to extract variables space of six (6) benchmark suites from MiBench. We have tested 290 small C programs (MIT corpus suite) having 22 different buffer overflow vulnerabilities in stack and heap. Experimental results show that our approach can detect buffer overflow attack with zero instruction overhead with the memory space requirement up to 13Kb to maintain VRT for a program with 324 variables.Comment: Accepted for publication in MWSCAS201

A Rare Case of Renal Gastrinoma

We present a rare case of renal gastrinoma. To the best of our knowledge, only one case of renal gastrinoma has been reported in the literature so far. An African American male was diagnosed with Zollinger Ellison syndrome at the age of 15 years, when he underwent surgery for peritonitis secondary to duodenal ulcer perforation. Further evaluation was deferred and proton pump inhibitors were prescribed. Later evaluation showed a left renal mass. Serum gastrin levels were 4,307 pg/ml. A CAT scan of the abdomen showed 4- x 4-cm heterogeneous solid mass in the interpolar region of the left kidney with central hypodensity. Somatostatin scintigraphy confirmed a receptor-positive mass in the same location. Nephrectomy was done and the tumor was diagnosed on histopathological examination as a gastrinoma. At 6-month follow-up, gastrin levels were 72 pg/ml. After a follow-up of 6 years, the patient has no recurrent symptoms

Architectural Power Estimation Based on Behavior Level Profiling

High level synthesis is the process of generating register transfer (RT) level designs from behavioral specifications. High level synthesis systems have traditionally taken into account such constraints as area, clock period and throughput time. Many high level synthesis systems [1] permit generation of many alternative RT level designs meeting these constraints in a relatively short time. If it is possible to accurately estimate the power consumption of RT level designs, then a low power design from among these alternatives can be selected.In this paper, we present an accurate power estimation technique for register transfer level designs generated by high level synthesis systems. The technique has four main aspects: (1) Each RT level component used in high level synthesis is characterized for average switched capacitance per input vector. This data is stored in the RT level component library. (2) Using user-specified stimuli, the given behavioral description is simulated and event activities of various operators and carriers are measured. Then, the behavioral specification is submitted to the synthesis system and a number of alternative RTL designs meeting speed, space and throughput rate constraints are generated. (3) Event activity of each component in an RT level design is estimated using the event activities measured at the time of behavior level profiling and the structure of the RTL design itself. (4) The event activities so obtained are then used to modulate the average switched capacitances of the respective RT level components to obtain an estimate the total switched capacitance of each component.Detailed power estimation procedures for the three different parts of RTL designs, namely, data path, controller and interconnect are presented. Experimental results obtained from a variety of designs show that the power estimates are within 3%–10% of the actual power measured by simulating the transistor level designs extracted from mask layouts